The present invention relates to programmable devices such as field programmable gate arrays (FPGAs). More specifically, the present invention relates to methods for programming watermarks in an FPGA.
Due to advancing semiconductor processing technology, integrated circuits have greatly increased in functionality and complexity. For example, programmable devices, such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs), can incorporate ever-increasing numbers of functional blocks and more flexible interconnect structures to provide greater functionality and flexibility.
FIG. 1 is a simplified schematic diagram of a conventional FPGA 110. FPGA 110 includes user logic circuits such as input/output blocks (IOBs), configurable logic blocks (CLBs), and programmable interconnect 130, which contains programmable switch matrices (PSMs). Each IOB and CLB can be configured through configuration port 120 to perform a variety of functions. Programmable interconnect 130 can be configured to provide electrical connections between the various CLBs and IOBs by configuring the PSMs and other programmable interconnection points (PIPS, not shown) through configuration port 120. Typically, the IOBs can be configured to drive output signals or to receive input signals from various pins (not shown) of FPGA 110.
FPGA 110 also includes dedicated internal logic. Dedicated internal logic performs specific functions and can only be minimally configured by a user. For example, configuration port 120 is one example of dedicated internal logic. Other examples may include dedicated clock nets (not shown), power distribution grids (not shown), and boundary scan logic (i.e., IEEE Boundary Scan Standard 1149.1, not shown).
FPGA 110 is illustrated with 16 CLBs, 16 IOBs, and 9 PSMs for clarity only. Actual FPGAs may contain thousands of CLBs, IOBs, and PSMs. The ratio of the number of CLBs, IOBs, and PSMs can also vary.
FPGA 110 also includes dedicated configuration logic circuits to program the user logic circuits. Specifically, each CLB, IOB, PSM, and PIP contains a configuration memory (not shown) which must be configured before each CLB, IOB, PSM, or PIP can perform a specified function. Typically, the configuration memories within an FPGA use static random access memory (SRAM) cells. The configuration memories of FPGA 110 are connected to configuration port 120 through a configuration structure (not shown) and a configuration access port (CAP) 125. Configuration port 120 (a set of pins used during the configuration process) provides an interface for external configuration devices to program the FPGA. The configuration memory is typically arranged in rows and columns. The columns are loaded from a frame register (part of the configuration structure referenced above) which is in turn sequentially loaded from one or more sequential bitstreams. In FPGA 110, configuration access port 125 is essentially a bus access point that provides access from configuration port 120 to the configuration structure of FPGA 110.
FIG. 2 illustrates a conventional structure used to configure FPGA 110. Specifically, FPGA 110 is coupled to a configuration device 230 such as a serial programmable read only memory (SPROM), an electrically programmable read only memory (EPROM), or a microprocessor. Configuration port 120 receives configuration data, usually in the form of a configuration bitstream, from configuration device 230. Typically, configuration port 120 contains a set of mode pins, a clock pin, and a configuration data input pin. Configuration data from configuration device 230 is transferred serially to FPGA 110 through a configuration data input pin (not shown) in configuration port 120. In some embodiments of FPGA 110, configuration port 120 comprises a set of configuration data input pins to increase the data transfer rate between configuration device 230 and FPGA 110 by transferring data in parallel. However, due to the limited number of dedicated function pins available on an FPGA, configuration port 120 usually has a relatively small number of configuration data input pins, e.g., eight or sixteen. Further, some FPGAs allow configuration through a boundary scan chain. Specific examples for configuring various FPGAs can be found on pages 6-60 to 6-68 of xe2x80x9cThe Programmable Logic Data Book 1999xe2x80x9d (hereinafter xe2x80x9cThe Xilinx 1999 Data Bookxe2x80x9d), published in March, 1999 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Additional methods to program FPGAs are described by Lawman in commonly assigned, co-pending U.S. patent application Ser. No. 09/000,519, entitled xe2x80x9cDECODER STRUCTURE AND METHOD FOR FPGA CONFIGURATIONxe2x80x9d by Gary R. Lawman, which is referenced above.
As explained above, actual FPGAs can have thousands of CLBs, IOBs, PSMs, and PIPs; therefore, the design and development of complex logic in FPGA 110 can be time-consuming and expensive. In order to simplify the design process and shorten the design cycle, many vendors provide macros for various functions that can be incorporated by an end user of the FPGA into the user""s own design file. For example, Xilinx, Inc. provides a PCI interface macro, which can be incorporated by an end user into the user""s design file. The user benefits from the macro because the user does not need to spend the time or resources to develop the complex logic included in the macro. Further, since the vendor profits from selling the same macro to many users, the vendor can spend the time and resources to design optimized macros. For example, the vendor strives to provide macros having high performance, flexibility, and low gate count. However, the macro vendors are reluctant to give out copies of the macros without a way of insuring that the macros are used only by licensed users. Thus, it has been proposed that FPGAs include embedded decryption circuits to decrypt encrypted macros. Alternatively, encrypted macros are decrypted prior to creation of the configuration bitstream. Both of these methods are described by Burnham et al. in commonly assigned, co-pending U.S. patent application Ser. No. 09/232,022, entitled xe2x80x9cMETHODS TO SECURELY CONFIGURE AN FPGA TO ACCEPT SELECTED MACROSxe2x80x9d by James L. Burnham, Gary R. Lawman, and Joseph D. Linoff, which is referenced above.
However, after a configuration device, such as configuration device 230, is programmed with a configuration bitstream, non-licensed users may illegally copy the configuration bitstream in configuration device 230 and make use of the macros without compensating the macro provider and/or the creator of the configuration bitstream. One method to deter copying of configuration data is to mark the configuration data with markers, also known as watermarks, within the configuration data stored in configuration device 230. Thus, if a macro provider suspects that a third party is using a macro without authorization, the macro provider can obtain a copy of the suspect configuration device and check for the watermark in the configuration bitstream to determine if the suspect configuration device contains the macro. Hence, there is a need for a method to watermark an FPGA macro in a configuration bitstream.
The present invention watermarks FPGA macros in configuration data so a macro provider can identify configuration data that includes a specific macro. Specifically, an end user creates a design file by incorporating a marked macro in the end user""s FPGA design file. The end user then uses an FPGA programming tool that is designed to detect marked macros and obtain watermarks from the marked macro, from the macro vendor, or from a watermark manager. The FPGA programming tool converts the design file into configuration data, which incorporates the macro and a watermark which identifies the macro. In one embodiment, the FPGA programming tool stores the watermark in unused portions of the configuration data. For example, the watermark may be stored in reserved locations of the configuration data, or in locations corresponding to unused user logic circuits. In some embodiments of the present invention, the marked macro reserves more user logic circuits than necessary, to ensure that unused logic is available for storing the watermark in the configuration data.